1. Field of the Invention
The present invention relates to a four-quadrant multiplier which multiplies two analog signals, and particularly to a multiplier constructed as a semiconductor integrated circuit using MOS (Metal Oxide Semiconductor) transistors or bipolar transistors.
2. Description of the Related Art
Multipliers are indispensable function blocks in the field of analog signal processing, and multipliers of a wide variety of circuit configurations have been proposed, including multipliers of circuit configuration suitable for incorporation in semiconductor integrated circuits (IC) or large-scale integrated circuits (LSI).
In recent years, with the advances in micro-scaled circuit patterns in the manufacture of IC and LSI, the power voltage of IC and LSI has fallen to 3.3 V or even 3 V from the usual conventional level of 5 V, therefore calling for multipliers that can operate at lower voltage. In addition, the growing recognition that CMOS (Complementary MOS) technology is best suited for LSI fabrication in turn calls for a circuit technology for realizing multipliers using a CMOS process.
However, multipliers that have been proposed to date do not in principle allow low-voltage operation, and moreover, have the drawback that satisfactory multiplier operation is possible over a narrow range of input voltage. The applicant of the present invention has proposed various types of four-quadrant multipliers that allow low-voltage operation, and moreover, provide excellent linearity over a wider range of input voltage (IEICE Transactions on Electronics, Vol. E76-C, No. 5, pp. 714-737, May 1993). The inventor has further endeavored to broaden the range of input operation voltage.